This invention relates generally to resistor-capacitor ("RC") equivalent and delay circuits. More particularly, the present invention relates to a circuit configuration for a CMOS RC equivalent delay circuit.
It is often desirable to use CMOS devices in analog circuit design wherever possible, since many integrated circuit chips involve CMOS processing. This is especially true when the size of the integrated circuit chip is an important engineering consideration. A typical prior art RC delay circuit includes N-well, N-plus, or P-plus resistors along with NMOS or PMOS capacitors. These circuit elements provide the desired electrical performance characteristics, but are relatively large, and therefore tend to take up a substantial amount of integrated circuit space. In turn, this can lead to unnecessarily large integrated circuit area, which adversely impacts unit cost.
What is desired is a CMOS RC equivalent delay circuit that takes up much less integrated circuit space than conventional CMOS RC circuits.